Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture

Triangles are the basic substructure of networks and triangle counting (TC) has been a fundamental graph computing problem in numerous fields such as social network analysis. Nevertheless, like other problems, due to high memory-computation ratio random memory access pattern, TC involves large amount data transfers thus suffers from bandwidth bottleneck traditional Von-Neumann architecture. To overcome this challenge, paper, we propose accelerate with emerging processing-in-memory (PIM) architecture through an algorithm-architecture co-optimization manner. enable efficient in-memory implementations, come up reformulate bitwise logic operations (such AND ), develop customized compression mapping techniques for flow management. With computational Spin-Transfer Torque Magnetic RAM (STT-MRAM) array, which is one most promising PIM enabling techniques, device-to-architecture co-simulation results demonstrate that proposed accelerator outperforms state-of-the-art GPU FPGA accelerations by $12.2\times$ notation="LaTeX">$31.8\times$ , respectively, achieves notation="LaTeX">$34\times$ energy efficiency improvement over accelerator.